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Phase-Locked Loops

Phase-locked loops (PLLs) are indispensable building blocks in modern electronic and communication systems. A PLL is a closed-loop system that seeks to synchronise the output of a controlled oscillator to an input signal. Our work on PLLs seeks to explain aspects of the behaviour of PLLs that cannot be explained by the application of conventional linear theory to what are inherently nonlinear systems.

Our work on PLLs focuses in particular on the effect of quantization – a hard. We characterise the limit cycle oscillations that arise as a result of this quantization in a variety of PLLs. For digital bang-bang PLLs, a class of PLLs employing binary phase-error quantization, we have applied stochastic analysis techniques to develop expressions for the output jitter performance of the loop in the presence of accumulative and non-accumulative clock jitter. We also identify and address certain problems in the existing treatment of the stability of charge-pump PLLs, through the application of methods of Lyapunov stability theory. We propose a new time-domain model for charge-pump PLLs that captures non-ideal effects in the charge pump and phase-frequency detector under high-speed operation.