Engineer in the Circuits and Systems Research Group

Position:

Engineer in the Circuits and Systems Research Group

School of Electrical and Electronic Engineering, University College Dublin

Start date – 1st September, 16 months

Salary – 34k pa

Supervisors – Dr Elena Blokhina (UCD) and Prof Dimitri Galayko (Sorbonne Univ.)

Description of the project:

The project responds to the challenge of high-precision (low jitter) phase and frequency synthesis in ubiquitous electronic component known as phase-locked loops. There are two larger classes of PLLs, which, in extreme cases, can be classified as having all or some analogue components (denoted in this project generally as PLLs) and implemented All-Di gitally (ADPLLs). It is generally accepted that the performance of ADPLLs is worse in the context of jitter than that of analogue PLLs. However, ADPLLs are easier to design, fabricate and integrate, and it gives certain advantages over their analogue counterparts. Hence the selection of the PLL type for specific applications is a choice based on various trade-offs. Analogue PLLs are still the system of choice if low phase noise/jitter signals are required. In this project we aim to show that the performance of ADPLL can be improved, making it comparable with analogue PLLs. In addition, a use of a distributedsignal generated in interconnected ADPLLs can be made for applications where delivering synchronous signals is important (synchronisation of SoCs, power reduction, etc.).

Required skills:

The successful candidate will be hosted at the School of Electrical and Electronic Engineering, University College Dublin (Ireland) and will work in the Circuits and Systems Research Group. The successful applicant must hold an Honours Master’s or PhD in Electronic Engineering. The candidate must be very well familiar with the concept of phase-locked loops, all-digital phase-locked loops and FPGAs since the project is on the system level design and optimization of the structural blocks of ADPPLs and implementation of additional circuitry in FPGA. 

Specific tasks allocated for the Engineer: (i) redesign of nodes (individual ADPLL) in a ADPLL network. In particular, the redesign will aim at a reduced resolution (and hence the size) of the Digitally Controlled Oscillator (DCO), a reduced linear range of the Time-To-Digital Converter (TDC) and, as a consequence, a simpler digital loop filter. Redesign of the loop filter (proportional-integral (PI) controller), DCO and TDC. (ii) Validation of the redesigned ADPLL and the simulation of the whole ADPLL with the use of the detailed models of the redesigned blocks at the transistor level. (iii) Implementation of the network of ADPLLs and a jitter reduction block on a selected FPGA platform; writing of the code necessary for implementation of the prototype; measurement and characterization.

It is expected that the candidate will have excellent communication skills, the ability to work well in an interdisciplinary team and will have experience working in Cadence.

How to apply:

Interested candidates should apply by  email to Dr. Elena Blokhina elena.blokhina@ucd.ie. Early applications are encouraged.

Applications should include:

  1.  a cover letter (1 page) explaining their interest in the project topic and mentioning any relevant background and/or experience;
  2.  a Curriculum Vitae. Academic transcripts and two academic references will be required after a shortlisting process takes place.